Semiconductor device fabrication requires that lithographic structures be transferred onto a wafer. It has long been understood that to facilitate such transfer, it is desirable to simplify lithographic patterns. For example, the prior art recommends avoiding as far as possible corners in the same lithographic plane.
Use of different channel widths of transistors is a common practice. The channel length of an MOSFET transistor is at the present time typically around 30 nm, whereas its width (W) is typically much greater. The width determines the current intensity in the transistor for given source, drain and gate voltages. Therefore, it is usually desirable to design an electronic circuit with transistors having different channel widths.
But, in practice, fabrication of different widths with precision can be difficult because of the resolution limits of lithography. In fact, although it is relatively easy to produce long strip-like structures by lithography, short strips of very controlled dimensions are particularly difficult to fabricate.
US patent application 2008/0251848 teaches a fabrication process aimed at obviating inhomogeneities in performance between the various transistors of a circuit. To do so, this document proposes to make the influence of the environment on the various transistors uniform. More precisely, this document provides that an array of FET transistors be arranged in the form of long strips. The drain and source regions of any one strip then have the same dimensions, being spaced apart by gate regions of fixed dimensions. This document is further described below
The resolution limit of the lithography tends to dictate the use of such long strips of transistors having identical dimensions. However, with long strips, the flexibility in designing electronic circuits is then lost since it is no longer possible to vary the geometric width of the various transistors so as to modulate their performance.
Transistors in digital integrated circuits are often organized into repeating patterns. In fact, the design of such integrated circuits is commonly based on integrating a plurality of elementary cells (similar cells often being stored together in a cell library) having predetermined logic functions. In general, two types of design may be distinguished.
According to the first type of design, an integrated circuit is constructed by selecting and interconnecting individual cells from a library comprising a large number, e.g., about a thousand, predesigned cells having simple functions, e.g., primitive Boolean logic functions (e.g., NAND, NOR and the like) and basic storage functions (e.g., latches, flip-flops and the like). Such cells providing simple functions and having simple implementation are often referred to as “standard cells”.
According to the second type of design, the cells are selected from a cell library providing cells specifically adapted to a particular circuit environment for which they are intended. Such cells providing more specialized functions and having more complex implementations are often referred to as “data-path” cells. Although data-path cells can be implemented by interconnecting standard cells, they are usually designed from scratch. In a given circuit, the use of data-path cells specifically developed for the environment of that particular circuit makes it possible to achieve better performance characteristics (typically in terms of speed, power consumption and footprint). However, the design cost is higher.
Thus, data-path cells are typically used only for high-speed circuits, for circuits requiring optimized performance characteristics, and the like. For example, microprocessors can be constructed from as an interconnected network of data-path cells. Often such a network is organized as one or more data-paths, which are typically linear arrangements of data-path cells that provide conduits for the flow and transformation of data. Data-path cells often found in a microprocessor include computational cells (e.g., multiplexers, shifters, adders, multipliers, and the like) and state elements (e.g., sequential circuits such as latches, register files and so like).
It is well known in the field of microelectronic devices, the field of application of the present invention, that improvements in performance (speed, power consumption and the like) and miniaturization are ongoing requirements. However, it is also well known that miniaturization can lead to problematic performance effects due to, e.g., short channel effects, small channel volume effects, and the like, and to the problematic fabrication effects already discussed that are due to, e.g., irregularities in photolithography of highly miniaturized patterns.
Accordingly, there is a need in the art for data-path cells that overcome such problems of miniaturization and provide improved performance and size characteristics and more reliable and simpler fabrication.